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[/] [dblclockfft/] [trunk/] [doc/] [src/] [gqtekspec.cls] - Rev 25

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Rev	Log message	Author	Age	Path
25	The documentation has been changed to bring it closer to the example specification document. The big change is that the first line, the headline if you will, of each table has een adjusted to have a gray background. The second and bigger change is in the fftgen software itself, or more specifically to the code that it produces. I had the opportunity to build the code using Xilinx's ISE and spent some time getting rid of warnings during the build. As a result, registers that need initial conditions now have initial conditions. In a similar manner I have trimmed out registers that were unused. The resulting code continues to pass all test benches, although I will admit that the automated testing of the whole fft or ifft via there test benches, fft_tb and ifft_tb, continues to be a less than automated process than it should be. Therefore, these test benches always "pass" and only a manual examination of the results can be used to confirm their success.	dgisselq	3508d 02h	/dblclockfft/trunk/doc/src/gqtekspec.cls
12	Minor changes to both class (trimmed the portlist and revision history tables to match the text width), and the description of the io ports. Specifically, i_left, the port that is broken out and described, had mislabeled/misnumbered bits in the port list. As this is a minor change, I will not update the revision--although perhaps it should be.	dgisselq	3549d 02h	/dblclockfft/trunk/doc/src/gqtekspec.cls
11	Here's the full first draft of the specification, now complete.	dgisselq	3549d 02h	/dblclockfft/trunk/doc/src/gqtekspec.cls
10	I'm in the middle of building the spec. I've got most of the parts complete, but the figure diagraming an FFT stage is still in the works. I'm checking this in in the hopes that someone struggling to use this will find this initial draft of the specification useful enough to make their project work.	dgisselq	3549d 14h	/dblclockfft/trunk/doc/src/gqtekspec.cls

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