URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga] - Rev 125

Rev	Log message	Author	Age	Path
125	hardware: cpu external pin ordering	hellwig	3791d 03h	/eco32/trunk/fpga
124	hardware: busctrl source formatted	hellwig	3791d 12h	/eco32/trunk/fpga
123	hardware: dsp now equivalent to port-15	hellwig	3791d 15h	/eco32/trunk/fpga
122	hardware: in sdramcntl.v signal added to sensitivity list	hellwig	3791d 21h	/eco32/trunk/fpga
121	hardware: dsk source formatted	hellwig	3792d 01h	/eco32/trunk/fpga
120	hardware: in cpu/sregs change signal names di->din, do->dout	hellwig	3792d 03h	/eco32/trunk/fpga
119	hardware: ram now equivalent to port-15	hellwig	3792d 13h	/eco32/trunk/fpga
118	hardware: rom now equivalent to port-15	hellwig	3793d 02h	/eco32/trunk/fpga
117	hardware: ser now equal to port-15	hellwig	3793d 21h	/eco32/trunk/fpga
116	hardware: kbd now equal to port-15	hellwig	3793d 22h	/eco32/trunk/fpga
81	hardware: cpu now has a bad address register	hellwig	3807d 05h	/eco32/trunk/fpga
77	hardware: ucf file re-formatted	hellwig	3810d 03h	/eco32/trunk/fpga
75	hardware: cpu now equal to port-15	hellwig	3810d 19h	/eco32/trunk/fpga
70	hardware: two timers	hellwig	3811d 19h	/eco32/trunk/fpga
69	hardware: timer counts clock cycles, counter is readable	hellwig	3811d 22h	/eco32/trunk/fpga
68	hardware: timer now equal to port-15	hellwig	3812d 02h	/eco32/trunk/fpga
67	fpga implementation update	hellwig	3812d 05h	/eco32/trunk/fpga
33	ISE project file again	hellwig	3816d 22h	/eco32/trunk/fpga
32	fpga config & startup options	hellwig	3816d 23h	/eco32/trunk/fpga
31	new ISE project file	hellwig	3816d 23h	/eco32/trunk/fpga