URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga] - Rev 311

Rev	Log message	Author	Age	Path
311	README updated	hellwig	3253d 22h	/eco32/trunk/fpga
310	verilated mc implementation with and without trace	hellwig	3254d 18h	/eco32/trunk/fpga
309	multicycle simulation of ECO32, using Verilator	hellwig	3255d 18h	/eco32/trunk/fpga
308	multicycle design, suitable for being verilated	hellwig	3255d 22h	/eco32/trunk/fpga
307	several tests got duration.dat files	hellwig	3256d 12h	/eco32/trunk/fpga
304	Makefile updated	hellwig	3259d 07h	/eco32/trunk/fpga
303	multicycle simulation control files added	hellwig	3259d 07h	/eco32/trunk/fpga
302	tests updated	hellwig	3259d 12h	/eco32/trunk/fpga
301	multicycle simulation source files added	hellwig	3259d 19h	/eco32/trunk/fpga
300	memdelay experiment code looking better now	hellwig	3259d 20h	/eco32/trunk/fpga
299	s3e-500 dac simulation corrected	hellwig	3259d 21h	/eco32/trunk/fpga
298	xsa-xst-3 dac simulation corrected	hellwig	3259d 21h	/eco32/trunk/fpga
297	memdelay experiment added	hellwig	3259d 22h	/eco32/trunk/fpga
296	memspeed experiment added	hellwig	3260d 10h	/eco32/trunk/fpga
295	tests for FPGA implementations	hellwig	3260d 21h	/eco32/trunk/fpga
292	directory structure for FPGA implementations and simulations	hellwig	3262d 12h	/eco32/trunk/fpga
291	avoid timing violations in DDR RAM circuit, new .bit files generated	hellwig	3262d 13h	/eco32/trunk/fpga
290	Wishbone-compatible bus signals	hellwig	3264d 14h	/eco32/trunk/fpga
289	new directory structure within fpga	hellwig	3265d 10h	/eco32/trunk/fpga
288	new directory structure within fpga	hellwig	3265d 11h	/eco32/trunk/fpga