URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga] - Rev 312

Rev	Log message	Author	Age	Path
312	memory controller simulation 0	hellwig	3283d 17h	/eco32/trunk/fpga
311	README updated	hellwig	3283d 18h	/eco32/trunk/fpga
310	verilated mc implementation with and without trace	hellwig	3284d 14h	/eco32/trunk/fpga
309	multicycle simulation of ECO32, using Verilator	hellwig	3285d 15h	/eco32/trunk/fpga
308	multicycle design, suitable for being verilated	hellwig	3285d 19h	/eco32/trunk/fpga
307	several tests got duration.dat files	hellwig	3286d 08h	/eco32/trunk/fpga
304	Makefile updated	hellwig	3289d 03h	/eco32/trunk/fpga
303	multicycle simulation control files added	hellwig	3289d 03h	/eco32/trunk/fpga
302	tests updated	hellwig	3289d 08h	/eco32/trunk/fpga
301	multicycle simulation source files added	hellwig	3289d 16h	/eco32/trunk/fpga
300	memdelay experiment code looking better now	hellwig	3289d 16h	/eco32/trunk/fpga
299	s3e-500 dac simulation corrected	hellwig	3289d 17h	/eco32/trunk/fpga
298	xsa-xst-3 dac simulation corrected	hellwig	3289d 17h	/eco32/trunk/fpga
297	memdelay experiment added	hellwig	3289d 18h	/eco32/trunk/fpga
296	memspeed experiment added	hellwig	3290d 07h	/eco32/trunk/fpga
295	tests for FPGA implementations	hellwig	3290d 18h	/eco32/trunk/fpga
292	directory structure for FPGA implementations and simulations	hellwig	3292d 09h	/eco32/trunk/fpga
291	avoid timing violations in DDR RAM circuit, new .bit files generated	hellwig	3292d 10h	/eco32/trunk/fpga
290	Wishbone-compatible bus signals	hellwig	3294d 10h	/eco32/trunk/fpga
289	new directory structure within fpga	hellwig	3295d 07h	/eco32/trunk/fpga