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[/] [eco32] - Rev 318

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Rev Log message Author Age Path
318 memory controller 1, FPGA realization hellwig 3342d 09h /eco32
317 README updated hellwig 3343d 00h /eco32
316 README added hellwig 3343d 03h /eco32
315 README added hellwig 3343d 04h /eco32
314 memory controller simulation 2 hellwig 3343d 05h /eco32
313 memory controller simulation 1 hellwig 3343d 07h /eco32
312 memory controller simulation 0 hellwig 3343d 08h /eco32
311 README updated hellwig 3343d 09h /eco32
310 verilated mc implementation with and without trace hellwig 3344d 06h /eco32
309 multicycle simulation of ECO32, using Verilator hellwig 3345d 06h /eco32
308 multicycle design, suitable for being verilated hellwig 3345d 10h /eco32
307 several tests got duration.dat files hellwig 3346d 00h /eco32
306 tool to show display output added hellwig 3346d 07h /eco32
305 tool to show serial output added hellwig 3346d 07h /eco32
304 Makefile updated hellwig 3348d 18h /eco32
303 multicycle simulation control files added hellwig 3348d 18h /eco32
302 tests updated hellwig 3348d 23h /eco32
301 multicycle simulation source files added hellwig 3349d 07h /eco32
300 memdelay experiment code looking better now hellwig 3349d 07h /eco32
299 s3e-500 dac simulation corrected hellwig 3349d 08h /eco32

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