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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_txstatem.v] - Rev 362

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4689d 22h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
352	Removed delayed assignments from rtl code	olof	4700d 23h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
346	Updated project location	olof	4711d 16h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
338		root	5515d 18h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
335	New directory structure.	root	5573d 00h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
276	Defer indication changed.	tadejm	7802d 20h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7894d 21h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
37	Link in the header changed.	mohor	8174d 23h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8271d 01h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
18	Few little NCSIM warnings fixed.	mohor	8308d 19h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8344d 19h	/ethmac/branches/unneback/rtl/verilog/eth_txstatem.v

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