URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 346

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
346	Updated project location	olof	4702d 04h	/ethmac/branches/unneback/rtl/verilog
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4712d 04h	/ethmac/branches/unneback/rtl/verilog
338		root	5506d 06h	/ethmac/branches/unneback/rtl/verilog
335	New directory structure.	root	5563d 12h	/ethmac/branches/unneback/rtl/verilog
333	Some small fixes + some troubles fixed.	igorm	7012d 02h	/ethmac/branches/unneback/rtl/verilog
332	Case statement improved for synthesys.	igorm	7025d 07h	/ethmac/branches/unneback/rtl/verilog
330	Warning fixes.	igorm	7040d 09h	/ethmac/branches/unneback/rtl/verilog
329	Defer indication fixed.	igorm	7040d 10h	/ethmac/branches/unneback/rtl/verilog
328	Delayed CRC fixed.	igorm	7040d 10h	/ethmac/branches/unneback/rtl/verilog
327	Defer indication fixed.	igorm	7040d 10h	/ethmac/branches/unneback/rtl/verilog
326	Delayed CRC fixed.	igorm	7040d 11h	/ethmac/branches/unneback/rtl/verilog
325	Defer indication fixed.	igorm	7040d 11h	/ethmac/branches/unneback/rtl/verilog
323	Accidently deleted line put back.	igorm	7337d 11h	/ethmac/branches/unneback/rtl/verilog
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7341d 06h	/ethmac/branches/unneback/rtl/verilog
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7341d 10h	/ethmac/branches/unneback/rtl/verilog
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7381d 12h	/ethmac/branches/unneback/rtl/verilog
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7484d 09h	/ethmac/branches/unneback/rtl/verilog
306	Lapsus fixed (!we -> ~we).	simons	7485d 07h	/ethmac/branches/unneback/rtl/verilog
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7507d 03h	/ethmac/branches/unneback/rtl/verilog
302	mbist signals updated according to newest convention	markom	7533d 14h	/ethmac/branches/unneback/rtl/verilog

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 346

Filtering Options