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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 40

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Rev	Log message	Author	Age	Path
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8322d 16h	/ethmac/branches/unneback/rtl/verilog
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8326d 20h	/ethmac/branches/unneback/rtl/verilog
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8335d 22h	/ethmac/branches/unneback/rtl/verilog
37	Link in the header changed.	mohor	8335d 22h	/ethmac/branches/unneback/rtl/verilog
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8384d 18h	/ethmac/branches/unneback/rtl/verilog
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 22h	/ethmac/branches/unneback/rtl/verilog
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 22h	/ethmac/branches/unneback/rtl/verilog
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8406d 18h	/ethmac/branches/unneback/rtl/verilog
24	Log file added.	mohor	8431d 21h	/ethmac/branches/unneback/rtl/verilog
23	Number of addresses (wb_adr_i) minimized.	mohor	8431d 21h	/ethmac/branches/unneback/rtl/verilog
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8432d 00h	/ethmac/branches/unneback/rtl/verilog
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8432d 21h	/ethmac/branches/unneback/rtl/verilog
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8456d 18h	/ethmac/branches/unneback/rtl/verilog
18	Few little NCSIM warnings fixed.	mohor	8469d 19h	/ethmac/branches/unneback/rtl/verilog
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8496d 19h	/ethmac/branches/unneback/rtl/verilog
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8504d 00h	/ethmac/branches/unneback/rtl/verilog
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8505d 18h	/ethmac/branches/unneback/rtl/verilog
14	Unconnected signals are now connected.	mohor	8509d 23h	/ethmac/branches/unneback/rtl/verilog
10	Directory structure changed. Files checked and joind together.	mohor	8512d 11h	/ethmac/branches/unneback/rtl/verilog

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