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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 46

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Rev	Log message	Author	Age	Path
46	HASH0 and HASH1 registers added.	mohor	8315d 15h	/ethmac/branches/unneback/rtl/verilog
43	Tx status is written back to the BD.	mohor	8316d 22h	/ethmac/branches/unneback/rtl/verilog
42	Rx status is written back to the BD.	mohor	8319d 15h	/ethmac/branches/unneback/rtl/verilog
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8321d 18h	/ethmac/branches/unneback/rtl/verilog
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8322d 15h	/ethmac/branches/unneback/rtl/verilog
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8326d 19h	/ethmac/branches/unneback/rtl/verilog
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8335d 21h	/ethmac/branches/unneback/rtl/verilog
37	Link in the header changed.	mohor	8335d 21h	/ethmac/branches/unneback/rtl/verilog
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8384d 17h	/ethmac/branches/unneback/rtl/verilog
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 21h	/ethmac/branches/unneback/rtl/verilog
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 21h	/ethmac/branches/unneback/rtl/verilog
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8406d 17h	/ethmac/branches/unneback/rtl/verilog
24	Log file added.	mohor	8431d 20h	/ethmac/branches/unneback/rtl/verilog
23	Number of addresses (wb_adr_i) minimized.	mohor	8431d 20h	/ethmac/branches/unneback/rtl/verilog
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8431d 23h	/ethmac/branches/unneback/rtl/verilog
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8432d 20h	/ethmac/branches/unneback/rtl/verilog
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8456d 17h	/ethmac/branches/unneback/rtl/verilog
18	Few little NCSIM warnings fixed.	mohor	8469d 17h	/ethmac/branches/unneback/rtl/verilog
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8496d 18h	/ethmac/branches/unneback/rtl/verilog
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8503d 23h	/ethmac/branches/unneback/rtl/verilog

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 46

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