URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 54

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
54	Addition of new module eth_addrcheck.v	billditt	8313d 12h	/ethmac/branches/unneback/rtl/verilog
53	Addition of new module eth_addrcheck.v	billditt	8313d 12h	/ethmac/branches/unneback/rtl/verilog
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8313d 12h	/ethmac/branches/unneback/rtl/verilog
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8313d 13h	/ethmac/branches/unneback/rtl/verilog
48	RxOverRun added to statuses.	mohor	8315d 16h	/ethmac/branches/unneback/rtl/verilog
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8315d 16h	/ethmac/branches/unneback/rtl/verilog
46	HASH0 and HASH1 registers added.	mohor	8315d 16h	/ethmac/branches/unneback/rtl/verilog
43	Tx status is written back to the BD.	mohor	8316d 23h	/ethmac/branches/unneback/rtl/verilog
42	Rx status is written back to the BD.	mohor	8319d 16h	/ethmac/branches/unneback/rtl/verilog
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8321d 19h	/ethmac/branches/unneback/rtl/verilog
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8322d 16h	/ethmac/branches/unneback/rtl/verilog
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8326d 20h	/ethmac/branches/unneback/rtl/verilog
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8335d 22h	/ethmac/branches/unneback/rtl/verilog
37	Link in the header changed.	mohor	8335d 22h	/ethmac/branches/unneback/rtl/verilog
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8384d 18h	/ethmac/branches/unneback/rtl/verilog
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 22h	/ethmac/branches/unneback/rtl/verilog
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8384d 22h	/ethmac/branches/unneback/rtl/verilog
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8406d 18h	/ethmac/branches/unneback/rtl/verilog
24	Log file added.	mohor	8431d 21h	/ethmac/branches/unneback/rtl/verilog
23	Number of addresses (wb_adr_i) minimized.	mohor	8431d 21h	/ethmac/branches/unneback/rtl/verilog

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog] - Rev 54

Filtering Options