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[/] [ethmac/] [branches/] [unneback/] [rtl] - Rev 218

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Rev Log message Author Age Path
218 Typo error fixed. (When using Bist) mohor 8067d 23h /ethmac/branches/unneback/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 8068d 20h /ethmac/branches/unneback/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 8068d 20h /ethmac/branches/unneback/rtl
212 Minor $display change. mohor 8068d 20h /ethmac/branches/unneback/rtl
211 Bist added. mohor 8068d 20h /ethmac/branches/unneback/rtl
210 BIST added. mohor 8068d 21h /ethmac/branches/unneback/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8085d 19h /ethmac/branches/unneback/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 8085d 19h /ethmac/branches/unneback/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 8088d 20h /ethmac/branches/unneback/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 8096d 22h /ethmac/branches/unneback/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 8097d 23h /ethmac/branches/unneback/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 8098d 23h /ethmac/branches/unneback/rtl
165 HASH improvement needed. mohor 8099d 02h /ethmac/branches/unneback/rtl
164 Ethernet debug registers removed. mohor 8099d 02h /ethmac/branches/unneback/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 8100d 00h /ethmac/branches/unneback/rtl
160 error acknowledge cycle termination added to display. mohor 8100d 00h /ethmac/branches/unneback/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 8100d 20h /ethmac/branches/unneback/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 8104d 18h /ethmac/branches/unneback/rtl
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 8104d 18h /ethmac/branches/unneback/rtl
148 Bug when last byte of destination address was not checked fixed. mohor 8104d 18h /ethmac/branches/unneback/rtl

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