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[/] [ethmac/] [branches/] [unneback/] [rtl] - Rev 250

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Rev Log message Author Age Path
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 8028d 06h /ethmac/branches/unneback/rtl
248 wb_rst_i is used for MIIM reset. mohor 8029d 06h /ethmac/branches/unneback/rtl
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 8032d 09h /ethmac/branches/unneback/rtl
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 8033d 05h /ethmac/branches/unneback/rtl
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 8034d 01h /ethmac/branches/unneback/rtl
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 8034d 01h /ethmac/branches/unneback/rtl
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 8034d 01h /ethmac/branches/unneback/rtl
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 8034d 02h /ethmac/branches/unneback/rtl
238 Defines fixed to use generic RAM by default. mohor 8046d 06h /ethmac/branches/unneback/rtl
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 8048d 11h /ethmac/branches/unneback/rtl
232 fpga define added. mohor 8054d 05h /ethmac/branches/unneback/rtl
229 case changed to casex. mohor 8060d 03h /ethmac/branches/unneback/rtl
227 Changed BIST scan signals. tadejm 8060d 07h /ethmac/branches/unneback/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 8060d 08h /ethmac/branches/unneback/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 8064d 08h /ethmac/branches/unneback/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 8067d 08h /ethmac/branches/unneback/rtl
218 Typo error fixed. (When using Bist) mohor 8067d 10h /ethmac/branches/unneback/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 8068d 07h /ethmac/branches/unneback/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 8068d 07h /ethmac/branches/unneback/rtl
212 Minor $display change. mohor 8068d 07h /ethmac/branches/unneback/rtl

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