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Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8201d 05h /ethmac/branches/unneback
83 MAC address recognition was not correct (bytes swaped). mohor 8201d 05h /ethmac/branches/unneback
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8201d 07h /ethmac/branches/unneback
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8201d 07h /ethmac/branches/unneback
80 Small fixes for external/internal DMA missmatches. mohor 8205d 09h /ethmac/branches/unneback
79 RetryCntLatched was unused and removed from design mohor 8205d 10h /ethmac/branches/unneback
78 WB_SEL_I was unused and removed from design mohor 8205d 10h /ethmac/branches/unneback
77 Interrupts changed mohor 8205d 10h /ethmac/branches/unneback
76 Interrupts changed in the top file mohor 8205d 10h /ethmac/branches/unneback
75 r_Bro is used for accepting/denying frames mohor 8205d 10h /ethmac/branches/unneback
74 Reset values are passed to registers through parameters mohor 8205d 10h /ethmac/branches/unneback
73 Number of interrupts changed mohor 8205d 10h /ethmac/branches/unneback
72 Retry is not activated when a Tx Underrun occured mohor 8209d 13h /ethmac/branches/unneback
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.		 mohor 8213d 15h /ethmac/branches/unneback
70 Small fixes. mohor 8213d 16h /ethmac/branches/unneback
69 Define missmatch fixed. mohor 8214d 13h /ethmac/branches/unneback
68 Registered trimmed. Unused registers removed. mohor 8215d 12h /ethmac/branches/unneback
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8215d 13h /ethmac/branches/unneback
66 Testbench fixed, code simplified, unused signals removed. mohor 8215d 19h /ethmac/branches/unneback
65 Testbench fixed, code simplified, unused signals removed. mohor 8215d 19h /ethmac/branches/unneback

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