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[/] [ethmac/] [tags/] [asyst_2] - Rev 124

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Rev Log message Author Age Path
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8010d 04h /ethmac/tags/asyst_2
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8012d 05h /ethmac/tags/asyst_2
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8012d 05h /ethmac/tags/asyst_2
120 Unused files removed. mohor 8012d 06h /ethmac/tags/asyst_2
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8012d 06h /ethmac/tags/asyst_2
118 ShiftEnded synchronization changed. mohor 8015d 21h /ethmac/tags/asyst_2
117 Clock mrx_clk set to 2.5 MHz. mohor 8016d 07h /ethmac/tags/asyst_2
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8016d 07h /ethmac/tags/asyst_2
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8017d 05h /ethmac/tags/asyst_2
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8018d 02h /ethmac/tags/asyst_2
113 RxPointer bug fixed. mohor 8024d 18h /ethmac/tags/asyst_2
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8025d 08h /ethmac/tags/asyst_2
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8025d 21h /ethmac/tags/asyst_2
110 m_wb_cyc_o signal released after every single transfer. mohor 8026d 00h /ethmac/tags/asyst_2
109 Comment removed. mohor 8026d 01h /ethmac/tags/asyst_2
108 Testbench supports unaligned accesses. mohor 8093d 11h /ethmac/tags/asyst_2
107 TX_BUF_BASE changed. mohor 8093d 11h /ethmac/tags/asyst_2
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8093d 11h /ethmac/tags/asyst_2
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8102d 12h /ethmac/tags/asyst_2
104 FCS should not be included in NibbleMinFl. mohor 8104d 06h /ethmac/tags/asyst_2

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