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[/] [ethmac/] [tags/] [asyst_3] - Rev 114

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Rev Log message Author Age Path
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8031d 20h /ethmac/tags/asyst_3
113 RxPointer bug fixed. mohor 8038d 12h /ethmac/tags/asyst_3
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8039d 02h /ethmac/tags/asyst_3
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8039d 15h /ethmac/tags/asyst_3
110 m_wb_cyc_o signal released after every single transfer. mohor 8039d 18h /ethmac/tags/asyst_3
109 Comment removed. mohor 8039d 19h /ethmac/tags/asyst_3
108 Testbench supports unaligned accesses. mohor 8107d 04h /ethmac/tags/asyst_3
107 TX_BUF_BASE changed. mohor 8107d 04h /ethmac/tags/asyst_3
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8107d 05h /ethmac/tags/asyst_3
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8116d 06h /ethmac/tags/asyst_3
104 FCS should not be included in NibbleMinFl. mohor 8118d 00h /ethmac/tags/asyst_3
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8118d 01h /ethmac/tags/asyst_3
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8118d 01h /ethmac/tags/asyst_3
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8118d 01h /ethmac/tags/asyst_3
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8118d 01h /ethmac/tags/asyst_3
99 Document revised. mohor 8125d 00h /ethmac/tags/asyst_3
98 Document revised. mohor 8125d 00h /ethmac/tags/asyst_3
97 Small typo fixed. lampret 8141d 22h /ethmac/tags/asyst_3
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8145d 22h /ethmac/tags/asyst_3
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8146d 01h /ethmac/tags/asyst_3

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