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[/] [ethmac/] [tags/] [rel_10/] [rtl/] [verilog] - Rev 238

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Rev	Log message	Author	Age	Path
238	Defines fixed to use generic RAM by default.	mohor	7901d 02h	/ethmac/tags/rel_10/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7903d 07h	/ethmac/tags/rel_10/rtl/verilog
232	fpga define added.	mohor	7909d 01h	/ethmac/tags/rel_10/rtl/verilog
229	case changed to casex.	mohor	7914d 23h	/ethmac/tags/rel_10/rtl/verilog
227	Changed BIST scan signals.	tadejm	7915d 03h	/ethmac/tags/rel_10/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7915d 04h	/ethmac/tags/rel_10/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7919d 04h	/ethmac/tags/rel_10/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7922d 05h	/ethmac/tags/rel_10/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7922d 07h	/ethmac/tags/rel_10/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7923d 03h	/ethmac/tags/rel_10/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7923d 03h	/ethmac/tags/rel_10/rtl/verilog
212	Minor $display change.	mohor	7923d 03h	/ethmac/tags/rel_10/rtl/verilog
211	Bist added.	mohor	7923d 04h	/ethmac/tags/rel_10/rtl/verilog
210	BIST added.	mohor	7923d 04h	/ethmac/tags/rel_10/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7940d 02h	/ethmac/tags/rel_10/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7940d 02h	/ethmac/tags/rel_10/rtl/verilog
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7943d 03h	/ethmac/tags/rel_10/rtl/verilog
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7951d 05h	/ethmac/tags/rel_10/rtl/verilog
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7952d 06h	/ethmac/tags/rel_10/rtl/verilog
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7953d 06h	/ethmac/tags/rel_10/rtl/verilog

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[/] [ethmac/] [tags/] [rel_10/] [rtl/] [verilog] - Rev 238

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