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[/] [ethmac/] [tags/] [rel_13/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 166

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166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7936d 19h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7936d 22h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7938d 16h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7942d 14h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7963d 13h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7983d 14h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7985d 17h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7989d 08h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7990d 17h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7998d 06h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7998d 20h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7999d 09h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7999d 12h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8066d 23h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8076d 00h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8101d 17h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8105d 17h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8111d 20h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8111d 20h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8121d 17h /ethmac/tags/rel_13/rtl/verilog/eth_wishbone.v

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