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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 352

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Rev Log message Author Age Path
338 root 5624d 02h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5681d 07h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7920d 05h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7980d 15h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7988d 19h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 8051d 02h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 8058d 23h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 8099d 23h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8194d 03h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8257d 07h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8260d 00h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8264d 08h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8267d 01h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8283d 07h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8379d 09h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8417d 03h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8453d 03h /ethmac/tags/rel_14/rtl/verilog/eth_macstatus.v

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