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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 350

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338 root 5496d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
335 New directory structure. root 5554d 00h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
287 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7649d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 7783d 19h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7783d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7791d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7792d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7793d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7852d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7853d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7855d 16h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7861d 11h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7887d 13h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7887d 17h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7887d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7891d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7894d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7895d 17h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7924d 19h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7925d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v

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