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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog] - Rev 82

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82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8148d 17h /ethmac/tags/rel_17/rtl/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
79 RetryCntLatched was unused and removed from design mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
78 WB_SEL_I was unused and removed from design mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
77 Interrupts changed mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
76 Interrupts changed in the top file mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
75 r_Bro is used for accepting/denying frames mohor 8152d 19h /ethmac/tags/rel_17/rtl/verilog
74 Reset values are passed to registers through parameters mohor 8152d 20h /ethmac/tags/rel_17/rtl/verilog
73 Number of interrupts changed mohor 8152d 20h /ethmac/tags/rel_17/rtl/verilog
72 Retry is not activated when a Tx Underrun occured mohor 8156d 23h /ethmac/tags/rel_17/rtl/verilog
70 Small fixes. mohor 8161d 01h /ethmac/tags/rel_17/rtl/verilog
69 Define missmatch fixed. mohor 8161d 22h /ethmac/tags/rel_17/rtl/verilog
68 Registered trimmed. Unused registers removed. mohor 8162d 22h /ethmac/tags/rel_17/rtl/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8162d 23h /ethmac/tags/rel_17/rtl/verilog
65 Testbench fixed, code simplified, unused signals removed. mohor 8163d 05h /ethmac/tags/rel_17/rtl/verilog
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8163d 19h /ethmac/tags/rel_17/rtl/verilog
63 RxAbort is connected differently. mohor 8163d 22h /ethmac/tags/rel_17/rtl/verilog
62 RxAbort is an output. No need to have is declared as wire. mohor 8163d 22h /ethmac/tags/rel_17/rtl/verilog
61 RxStartFrm cleared when abort or retry comes. mohor 8164d 00h /ethmac/tags/rel_17/rtl/verilog
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8164d 00h /ethmac/tags/rel_17/rtl/verilog

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