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[/] [ethmac/] [tags/] [rel_17] - Rev 227

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Rev Log message Author Age Path
227 Changed BIST scan signals. tadejm 7904d 16h /ethmac/tags/rel_17
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7904d 18h /ethmac/tags/rel_17
225 Some minor changes. tadejm 7904d 18h /ethmac/tags/rel_17
224 Signals for a wave window in Modelsim. tadejm 7904d 19h /ethmac/tags/rel_17
223 Some code changed due to bug fixes. tadejm 7904d 19h /ethmac/tags/rel_17
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7908d 17h /ethmac/tags/rel_17
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7911d 18h /ethmac/tags/rel_17
218 Typo error fixed. (When using Bist) mohor 7911d 20h /ethmac/tags/rel_17
217 Bist supported. mohor 7911d 20h /ethmac/tags/rel_17
216 Bist signals added. mohor 7911d 20h /ethmac/tags/rel_17
215 Bist supported. mohor 7911d 21h /ethmac/tags/rel_17
214 Signals for WISHBONE B3 compliant interface added. mohor 7912d 16h /ethmac/tags/rel_17
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7912d 17h /ethmac/tags/rel_17
212 Minor $display change. mohor 7912d 17h /ethmac/tags/rel_17
211 Bist added. mohor 7912d 17h /ethmac/tags/rel_17
210 BIST added. mohor 7912d 17h /ethmac/tags/rel_17
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7913d 20h /ethmac/tags/rel_17
208 Virtual Silicon RAMs moved to lib directory tadej 7929d 14h /ethmac/tags/rel_17
207 Virtual Silicon RAM support fixed tadej 7929d 14h /ethmac/tags/rel_17
206 Virtual Silicon RAM added to the simulation. mohor 7929d 14h /ethmac/tags/rel_17

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