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[/] [ethmac/] [tags/] [rel_18] - Rev 236

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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7888d 15h /ethmac/tags/rel_18
235 rev 4. mohor 7889d 06h /ethmac/tags/rel_18
234 Figure list assed to the revision 3. mohor 7889d 14h /ethmac/tags/rel_18
233 Revision 0.3 released. Some figures added. mohor 7889d 14h /ethmac/tags/rel_18
232 fpga define added. mohor 7894d 09h /ethmac/tags/rel_18
231 Description of Core Modules added (figure). mohor 7896d 10h /ethmac/tags/rel_18
229 case changed to casex. mohor 7900d 07h /ethmac/tags/rel_18
227 Changed BIST scan signals. tadejm 7900d 11h /ethmac/tags/rel_18
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7900d 12h /ethmac/tags/rel_18
225 Some minor changes. tadejm 7900d 12h /ethmac/tags/rel_18
224 Signals for a wave window in Modelsim. tadejm 7900d 14h /ethmac/tags/rel_18
223 Some code changed due to bug fixes. tadejm 7900d 14h /ethmac/tags/rel_18
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7904d 12h /ethmac/tags/rel_18
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7907d 12h /ethmac/tags/rel_18
218 Typo error fixed. (When using Bist) mohor 7907d 14h /ethmac/tags/rel_18
217 Bist supported. mohor 7907d 14h /ethmac/tags/rel_18
216 Bist signals added. mohor 7907d 14h /ethmac/tags/rel_18
215 Bist supported. mohor 7907d 15h /ethmac/tags/rel_18
214 Signals for WISHBONE B3 compliant interface added. mohor 7908d 11h /ethmac/tags/rel_18
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7908d 11h /ethmac/tags/rel_18

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