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Rev Log message Author Age Path
218 Typo error fixed. (When using Bist) mohor 7970d 06h /ethmac/tags/rel_19
217 Bist supported. mohor 7970d 06h /ethmac/tags/rel_19
216 Bist signals added. mohor 7970d 06h /ethmac/tags/rel_19
215 Bist supported. mohor 7970d 07h /ethmac/tags/rel_19
214 Signals for WISHBONE B3 compliant interface added. mohor 7971d 03h /ethmac/tags/rel_19
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7971d 03h /ethmac/tags/rel_19
212 Minor $display change. mohor 7971d 03h /ethmac/tags/rel_19
211 Bist added. mohor 7971d 03h /ethmac/tags/rel_19
210 BIST added. mohor 7971d 03h /ethmac/tags/rel_19
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7972d 06h /ethmac/tags/rel_19
208 Virtual Silicon RAMs moved to lib directory tadej 7988d 00h /ethmac/tags/rel_19
207 Virtual Silicon RAM support fixed tadej 7988d 00h /ethmac/tags/rel_19
206 Virtual Silicon RAM added to the simulation. mohor 7988d 01h /ethmac/tags/rel_19
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7988d 01h /ethmac/tags/rel_19
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7988d 01h /ethmac/tags/rel_19
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7988d 01h /ethmac/tags/rel_19
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7991d 02h /ethmac/tags/rel_19
201 Core size added to the document. mohor 7991d 03h /ethmac/tags/rel_19
200 File with lower case checked in instead. mohor 7991d 03h /ethmac/tags/rel_19
199 Datasheet name changed to lower case name. mohor 7991d 03h /ethmac/tags/rel_19

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