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[/] [ethmac/] [tags/] [rel_20] - Rev 240

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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7864d 22h /ethmac/tags/rel_20
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7864d 22h /ethmac/tags/rel_20
238 Defines fixed to use generic RAM by default. mohor 7877d 02h /ethmac/tags/rel_20
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7879d 08h /ethmac/tags/rel_20
235 rev 4. mohor 7879d 22h /ethmac/tags/rel_20
234 Figure list assed to the revision 3. mohor 7880d 06h /ethmac/tags/rel_20
233 Revision 0.3 released. Some figures added. mohor 7880d 07h /ethmac/tags/rel_20
232 fpga define added. mohor 7885d 02h /ethmac/tags/rel_20
231 Description of Core Modules added (figure). mohor 7887d 03h /ethmac/tags/rel_20
229 case changed to casex. mohor 7891d 00h /ethmac/tags/rel_20
227 Changed BIST scan signals. tadejm 7891d 03h /ethmac/tags/rel_20
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7891d 05h /ethmac/tags/rel_20
225 Some minor changes. tadejm 7891d 05h /ethmac/tags/rel_20
224 Signals for a wave window in Modelsim. tadejm 7891d 06h /ethmac/tags/rel_20
223 Some code changed due to bug fixes. tadejm 7891d 06h /ethmac/tags/rel_20
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7895d 04h /ethmac/tags/rel_20
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7898d 05h /ethmac/tags/rel_20
218 Typo error fixed. (When using Bist) mohor 7898d 07h /ethmac/tags/rel_20
217 Bist supported. mohor 7898d 07h /ethmac/tags/rel_20
216 Bist signals added. mohor 7898d 07h /ethmac/tags/rel_20

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