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[/] [ethmac/] [tags/] [rel_23/] [bench/] [verilog] - Rev 178

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Rev Log message Author Age Path
178 Rearanged testcases mohor 8007d 01h /ethmac/tags/rel_23/bench/verilog
177 Bug in MIIM fixed. mohor 8007d 05h /ethmac/tags/rel_23/bench/verilog
170 Headers changed. mohor 8007d 07h /ethmac/tags/rel_23/bench/verilog
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8007d 07h /ethmac/tags/rel_23/bench/verilog
158 Typo fixed. mohor 8012d 03h /ethmac/tags/rel_23/bench/verilog
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8014d 08h /ethmac/tags/rel_23/bench/verilog
156 Valid testbench. mohor 8014d 08h /ethmac/tags/rel_23/bench/verilog
155 Minor changes. mohor 8014d 08h /ethmac/tags/rel_23/bench/verilog
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8057d 02h /ethmac/tags/rel_23/bench/verilog
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8059d 03h /ethmac/tags/rel_23/bench/verilog
117 Clock mrx_clk set to 2.5 MHz. mohor 8063d 05h /ethmac/tags/rel_23/bench/verilog
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8063d 05h /ethmac/tags/rel_23/bench/verilog
108 Testbench supports unaligned accesses. mohor 8140d 09h /ethmac/tags/rel_23/bench/verilog
107 TX_BUF_BASE changed. mohor 8140d 09h /ethmac/tags/rel_23/bench/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8185d 06h /ethmac/tags/rel_23/bench/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8206d 02h /ethmac/tags/rel_23/bench/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8216d 06h /ethmac/tags/rel_23/bench/verilog
66 Testbench fixed, code simplified, unused signals removed. mohor 8216d 12h /ethmac/tags/rel_23/bench/verilog
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8217d 23h /ethmac/tags/rel_23/bench/verilog
49 HASH0 and HASH1 register read/write added. mohor 8219d 23h /ethmac/tags/rel_23/bench/verilog

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