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[/] [ethmac/] [tags/] [rel_23/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 342

Rev	Log message	Author	Age	Path
338		root	5521d 17h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
335	New directory structure.	root	5578d 22h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
305	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7522d 14h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7522d 14h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7549d 00h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7612d 15h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7912d 15h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7920d 15h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7937d 14h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7999d 15h	/ethmac/tags/rel_23/rtl/verilog/eth_spram_256x32.v