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Rev Log message Author Age Path
245 Rev 1.7. mohor 7889d 09h /ethmac/tags/rel_23
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7889d 11h /ethmac/tags/rel_23
243 Late collision is not reported any more. tadejm 7889d 16h /ethmac/tags/rel_23
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7890d 07h /ethmac/tags/rel_23
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7890d 07h /ethmac/tags/rel_23
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7890d 07h /ethmac/tags/rel_23
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7890d 07h /ethmac/tags/rel_23
238 Defines fixed to use generic RAM by default. mohor 7902d 11h /ethmac/tags/rel_23
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7904d 17h /ethmac/tags/rel_23
235 rev 4. mohor 7905d 07h /ethmac/tags/rel_23
234 Figure list assed to the revision 3. mohor 7905d 16h /ethmac/tags/rel_23
233 Revision 0.3 released. Some figures added. mohor 7905d 16h /ethmac/tags/rel_23
232 fpga define added. mohor 7910d 11h /ethmac/tags/rel_23
231 Description of Core Modules added (figure). mohor 7912d 12h /ethmac/tags/rel_23
229 case changed to casex. mohor 7916d 09h /ethmac/tags/rel_23
227 Changed BIST scan signals. tadejm 7916d 13h /ethmac/tags/rel_23
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7916d 14h /ethmac/tags/rel_23
225 Some minor changes. tadejm 7916d 14h /ethmac/tags/rel_23
224 Signals for a wave window in Modelsim. tadejm 7916d 15h /ethmac/tags/rel_23
223 Some code changed due to bug fixes. tadejm 7916d 16h /ethmac/tags/rel_23

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