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[/] [ethmac/] [tags/] [rel_24/] - Rev 236

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Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7894d 20h /ethmac/tags/rel_24
235 rev 4. mohor 7895d 11h /ethmac/tags/rel_24
234 Figure list assed to the revision 3. mohor 7895d 19h /ethmac/tags/rel_24
233 Revision 0.3 released. Some figures added. mohor 7895d 19h /ethmac/tags/rel_24
232 fpga define added. mohor 7900d 14h /ethmac/tags/rel_24
231 Description of Core Modules added (figure). mohor 7902d 16h /ethmac/tags/rel_24
229 case changed to casex. mohor 7906d 12h /ethmac/tags/rel_24
227 Changed BIST scan signals. tadejm 7906d 16h /ethmac/tags/rel_24
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7906d 18h /ethmac/tags/rel_24
225 Some minor changes. tadejm 7906d 18h /ethmac/tags/rel_24
224 Signals for a wave window in Modelsim. tadejm 7906d 19h /ethmac/tags/rel_24
223 Some code changed due to bug fixes. tadejm 7906d 19h /ethmac/tags/rel_24
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7910d 17h /ethmac/tags/rel_24
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7913d 18h /ethmac/tags/rel_24
218 Typo error fixed. (When using Bist) mohor 7913d 20h /ethmac/tags/rel_24
217 Bist supported. mohor 7913d 20h /ethmac/tags/rel_24
216 Bist signals added. mohor 7913d 20h /ethmac/tags/rel_24
215 Bist supported. mohor 7913d 21h /ethmac/tags/rel_24
214 Signals for WISHBONE B3 compliant interface added. mohor 7914d 16h /ethmac/tags/rel_24
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7914d 17h /ethmac/tags/rel_24

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