URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 239

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7870d 22h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7896d 23h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7897d 03h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7897d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7901d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7904d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	7905d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7934d 06h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7935d 06h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
164	Ethernet debug registers removed.	mohor	7935d 09h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7937d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7941d 01h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7962d 01h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7982d 02h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7984d 05h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7987d 19h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7989d 04h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7996d 17h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7997d 07h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7997d 20h	/ethmac/tags/rel_24/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 239

Filtering Options