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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] [tb_ethernet.v] - Rev 260

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Rev Log message Author Age Path
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7869d 08h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7871d 01h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7871d 04h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7876d 08h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7903d 05h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7903d 08h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7912d 08h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7931d 07h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7933d 04h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7935d 04h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7935d 07h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7938d 02h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7938d 03h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7938d 03h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7938d 07h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7938d 09h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7938d 10h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7943d 05h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7945d 11h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7990d 05h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v

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