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[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog] - Rev 242

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Rev	Log message	Author	Age	Path
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7918d 22h	/ethmac/tags/rel_27/rtl/verilog
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7918d 22h	/ethmac/tags/rel_27/rtl/verilog
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7918d 22h	/ethmac/tags/rel_27/rtl/verilog
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7918d 22h	/ethmac/tags/rel_27/rtl/verilog
238	Defines fixed to use generic RAM by default.	mohor	7931d 02h	/ethmac/tags/rel_27/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7933d 07h	/ethmac/tags/rel_27/rtl/verilog
232	fpga define added.	mohor	7939d 01h	/ethmac/tags/rel_27/rtl/verilog
229	case changed to casex.	mohor	7944d 23h	/ethmac/tags/rel_27/rtl/verilog
227	Changed BIST scan signals.	tadejm	7945d 03h	/ethmac/tags/rel_27/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7945d 05h	/ethmac/tags/rel_27/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7949d 04h	/ethmac/tags/rel_27/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7952d 05h	/ethmac/tags/rel_27/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7952d 07h	/ethmac/tags/rel_27/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7953d 03h	/ethmac/tags/rel_27/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7953d 03h	/ethmac/tags/rel_27/rtl/verilog
212	Minor $display change.	mohor	7953d 04h	/ethmac/tags/rel_27/rtl/verilog
211	Bist added.	mohor	7953d 04h	/ethmac/tags/rel_27/rtl/verilog
210	BIST added.	mohor	7953d 04h	/ethmac/tags/rel_27/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7970d 02h	/ethmac/tags/rel_27/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7970d 02h	/ethmac/tags/rel_27/rtl/verilog

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[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog] - Rev 242

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