OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_5/] [rtl/] [verilog/] [eth_top.v] - Rev 202

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7936d 11h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7944d 13h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7946d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7947d 15h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7952d 09h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7993d 10h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8001d 09h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8076d 18h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8087d 14h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8115d 15h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8142d 11h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8142d 12h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
70 Small fixes. mohor 8150d 17h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8152d 14h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8152d 15h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8152d 21h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8153d 14h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8153d 16h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8154d 08h /ethmac/tags/rel_5/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8156d 11h /ethmac/tags/rel_5/rtl/verilog/eth_top.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.