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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 82

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82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8142d 09h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8146d 11h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8146d 12h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8157d 11h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8157d 16h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8157d 16h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8158d 07h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8160d 11h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
43 Tx status is written back to the BD. mohor 8161d 19h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
42 Rx status is written back to the BD. mohor 8164d 12h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8166d 14h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8167d 11h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8171d 15h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8180d 17h /ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v

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