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Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8266d 13h /ethmac/tags/rel_7
83 MAC address recognition was not correct (bytes swaped). mohor 8266d 13h /ethmac/tags/rel_7
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8266d 15h /ethmac/tags/rel_7
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8266d 15h /ethmac/tags/rel_7
80 Small fixes for external/internal DMA missmatches. mohor 8270d 17h /ethmac/tags/rel_7
79 RetryCntLatched was unused and removed from design mohor 8270d 17h /ethmac/tags/rel_7
78 WB_SEL_I was unused and removed from design mohor 8270d 17h /ethmac/tags/rel_7
77 Interrupts changed mohor 8270d 18h /ethmac/tags/rel_7
76 Interrupts changed in the top file mohor 8270d 18h /ethmac/tags/rel_7
75 r_Bro is used for accepting/denying frames mohor 8270d 18h /ethmac/tags/rel_7
74 Reset values are passed to registers through parameters mohor 8270d 18h /ethmac/tags/rel_7
73 Number of interrupts changed mohor 8270d 18h /ethmac/tags/rel_7
72 Retry is not activated when a Tx Underrun occured mohor 8274d 21h /ethmac/tags/rel_7
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.		 mohor 8278d 22h /ethmac/tags/rel_7
70 Small fixes. mohor 8278d 23h /ethmac/tags/rel_7
69 Define missmatch fixed. mohor 8279d 20h /ethmac/tags/rel_7
68 Registered trimmed. Unused registers removed. mohor 8280d 20h /ethmac/tags/rel_7
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8280d 21h /ethmac/tags/rel_7
66 Testbench fixed, code simplified, unused signals removed. mohor 8281d 03h /ethmac/tags/rel_7
65 Testbench fixed, code simplified, unused signals removed. mohor 8281d 03h /ethmac/tags/rel_7

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