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[/] [ethmac/] [tags/] [rel_9/] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7900d 18h /ethmac/tags/rel_9
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7903d 19h /ethmac/tags/rel_9
218 Typo error fixed. (When using Bist) mohor 7903d 21h /ethmac/tags/rel_9
217 Bist supported. mohor 7903d 21h /ethmac/tags/rel_9
216 Bist signals added. mohor 7903d 21h /ethmac/tags/rel_9
215 Bist supported. mohor 7903d 22h /ethmac/tags/rel_9
214 Signals for WISHBONE B3 compliant interface added. mohor 7904d 17h /ethmac/tags/rel_9
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7904d 17h /ethmac/tags/rel_9
212 Minor $display change. mohor 7904d 17h /ethmac/tags/rel_9
211 Bist added. mohor 7904d 18h /ethmac/tags/rel_9
210 BIST added. mohor 7904d 18h /ethmac/tags/rel_9
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7905d 21h /ethmac/tags/rel_9
208 Virtual Silicon RAMs moved to lib directory tadej 7921d 15h /ethmac/tags/rel_9
207 Virtual Silicon RAM support fixed tadej 7921d 15h /ethmac/tags/rel_9
206 Virtual Silicon RAM added to the simulation. mohor 7921d 15h /ethmac/tags/rel_9
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7921d 16h /ethmac/tags/rel_9
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7921d 16h /ethmac/tags/rel_9
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7921d 16h /ethmac/tags/rel_9
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7924d 17h /ethmac/tags/rel_9
201 Core size added to the document. mohor 7924d 18h /ethmac/tags/rel_9

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