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[/] [ethmac/] [trunk/] [bench/] [verilog] - Rev 181

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Rev Log message Author Age Path
181 MIIM test look better. mohor 7921d 18h /ethmac/trunk/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7924d 14h /ethmac/trunk/bench/verilog
179 Beautiful tests merget together mohor 7924d 14h /ethmac/trunk/bench/verilog
178 Rearanged testcases mohor 7924d 14h /ethmac/trunk/bench/verilog
177 Bug in MIIM fixed. mohor 7924d 18h /ethmac/trunk/bench/verilog
170 Headers changed. mohor 7924d 20h /ethmac/trunk/bench/verilog
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7924d 21h /ethmac/trunk/bench/verilog
158 Typo fixed. mohor 7929d 17h /ethmac/trunk/bench/verilog
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7931d 22h /ethmac/trunk/bench/verilog
156 Valid testbench. mohor 7931d 22h /ethmac/trunk/bench/verilog
155 Minor changes. mohor 7931d 22h /ethmac/trunk/bench/verilog
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7974d 16h /ethmac/trunk/bench/verilog
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7976d 16h /ethmac/trunk/bench/verilog
117 Clock mrx_clk set to 2.5 MHz. mohor 7980d 19h /ethmac/trunk/bench/verilog
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7980d 19h /ethmac/trunk/bench/verilog
108 Testbench supports unaligned accesses. mohor 8057d 22h /ethmac/trunk/bench/verilog
107 TX_BUF_BASE changed. mohor 8057d 22h /ethmac/trunk/bench/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8102d 20h /ethmac/trunk/bench/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8123d 16h /ethmac/trunk/bench/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8133d 20h /ethmac/trunk/bench/verilog

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