URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog] - Rev 19

Rev	Log message	Author	Age	Path
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8449d 21h	/ethmac/trunk/bench/verilog
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8489d 22h	/ethmac/trunk/bench/verilog
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8498d 21h	/ethmac/trunk/bench/verilog
12	Directory structure changed. Files checked and joind together.	mohor	8505d 14h	/ethmac/trunk/bench/verilog