URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Rev 365

Rev	Log message	Author	Age	Path
365	Whitespace cleanup	olof	4855d 16h	/ethmac/trunk/rtl/verilog/eth_fifo.v
357	Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC	olof	4861d 13h	/ethmac/trunk/rtl/verilog/eth_fifo.v
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4861d 15h	/ethmac/trunk/rtl/verilog/eth_fifo.v
354	Whitespace cleanup	olof	4861d 16h	/ethmac/trunk/rtl/verilog/eth_fifo.v
352	Removed delayed assignments from rtl code	olof	4868d 00h	/ethmac/trunk/rtl/verilog/eth_fifo.v
346	Updated project location	olof	4878d 16h	/ethmac/trunk/rtl/verilog/eth_fifo.v
338		root	5682d 19h	/ethmac/trunk/rtl/verilog/eth_fifo.v
335	New directory structure.	root	5740d 00h	/ethmac/trunk/rtl/verilog/eth_fifo.v
330	Warning fixes.	igorm	7216d 21h	/ethmac/trunk/rtl/verilog/eth_fifo.v
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8252d 20h	/ethmac/trunk/rtl/verilog/eth_fifo.v
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8280d 20h	/ethmac/trunk/rtl/verilog/eth_fifo.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8328d 17h	/ethmac/trunk/rtl/verilog/eth_fifo.v