OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 365

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 4697d 02h /ethmac/trunk/rtl/verilog/eth_macstatus.v
346 Updated project location olof 4707d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
338 root 5511d 21h /ethmac/trunk/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5569d 02h /ethmac/trunk/rtl/verilog/eth_macstatus.v
333 Some small fixes + some troubles fixed. igorm 7017d 16h /ethmac/trunk/rtl/verilog/eth_macstatus.v
325 Defer indication fixed. igorm 7046d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 7798d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7868d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7876d 13h /ethmac/trunk/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7938d 21h /ethmac/trunk/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7946d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 7987d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8081d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8145d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8147d 19h /ethmac/trunk/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8152d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8154d 20h /ethmac/trunk/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8171d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8267d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8304d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.