OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 368

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4685d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4685d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4685d 13h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
354 Whitespace cleanup olof 4685d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4691d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4702d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 5506d 17h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5563d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 7040d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7484d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7485d 17h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7507d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7534d 00h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7597d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 7897d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 7905d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7922d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7984d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.