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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 368

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Rev	Log message	Author	Age	Path
368	dbg_dat0 only exist when `DEBUG_WISHBONE is set	olof	4668d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
367	Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored	olof	4731d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
360	Added partial implementation of the debug register from ORPSoC	olof	4858d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
359	Verilator linting fixes	olof	4860d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
358	Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version	olof	4862d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4862d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
355	Import Julius Baxter's verilator hints from ORPSoC	olof	4862d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
354	Whitespace cleanup	olof	4862d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
352	Removed delayed assignments from rtl code	olof	4868d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
349	Make all parameters configurable from top level	olof	4878d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
346	Updated project location	olof	4879d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
338		root	5683d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5740d 12h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
333	Some small fixes + some troubles fixed.	igorm	7189d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
329	Defer indication fixed.	igorm	7217d 10h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
323	Accidently deleted line put back.	igorm	7514d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7518d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7684d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
302	mbist signals updated according to newest convention	markom	7710d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
280	Reset has priority in some flipflops.	mohor	7970d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 368

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