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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 367

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Rev	Log message	Author	Age	Path
367	Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored	olof	4756d 19h	/ethmac/trunk/rtl/verilog/ethmac.v
365	Whitespace cleanup	olof	4881d 22h	/ethmac/trunk/rtl/verilog/ethmac.v
364	Renamed eth_top.v to ethmac.v to fit better into OpenCores structure	olof	4882d 20h	/ethmac/trunk/rtl/verilog/ethmac.v
360	Added partial implementation of the debug register from ORPSoC	olof	4884d 03h	/ethmac/trunk/rtl/verilog/eth_top.v
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4887d 21h	/ethmac/trunk/rtl/verilog/eth_top.v
352	Removed delayed assignments from rtl code	olof	4894d 06h	/ethmac/trunk/rtl/verilog/eth_top.v
349	Make all parameters configurable from top level	olof	4903d 21h	/ethmac/trunk/rtl/verilog/eth_top.v
346	Updated project location	olof	4904d 23h	/ethmac/trunk/rtl/verilog/eth_top.v
338		root	5709d 01h	/ethmac/trunk/rtl/verilog/eth_top.v
335	New directory structure.	root	5766d 06h	/ethmac/trunk/rtl/verilog/eth_top.v
333	Some small fixes + some troubles fixed.	igorm	7214d 20h	/ethmac/trunk/rtl/verilog/eth_top.v
327	Defer indication fixed.	igorm	7243d 05h	/ethmac/trunk/rtl/verilog/eth_top.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7544d 01h	/ethmac/trunk/rtl/verilog/eth_top.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7709d 22h	/ethmac/trunk/rtl/verilog/eth_top.v
302	mbist signals updated according to newest convention	markom	7736d 09h	/ethmac/trunk/rtl/verilog/eth_top.v
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7747d 01h	/ethmac/trunk/rtl/verilog/eth_top.v
276	Defer indication changed.	tadejm	7996d 03h	/ethmac/trunk/rtl/verilog/eth_top.v
272	When control packets were received, they were ignored in some cases.	tadejm	8004d 03h	/ethmac/trunk/rtl/verilog/eth_top.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	8005d 04h	/ethmac/trunk/rtl/verilog/eth_top.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	8065d 14h	/ethmac/trunk/rtl/verilog/eth_top.v

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 367

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