URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 202

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7932d 07h	/ethmac/trunk/rtl/verilog/ethmac.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7940d 09h	/ethmac/trunk/rtl/verilog/ethmac.v
164	Ethernet debug registers removed.	mohor	7942d 14h	/ethmac/trunk/rtl/verilog/ethmac.v
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7943d 11h	/ethmac/trunk/rtl/verilog/ethmac.v
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7948d 05h	/ethmac/trunk/rtl/verilog/ethmac.v
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7989d 06h	/ethmac/trunk/rtl/verilog/ethmac.v
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7997d 05h	/ethmac/trunk/rtl/verilog/ethmac.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8072d 14h	/ethmac/trunk/rtl/verilog/ethmac.v
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8083d 10h	/ethmac/trunk/rtl/verilog/ethmac.v
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8111d 11h	/ethmac/trunk/rtl/verilog/ethmac.v
80	Small fixes for external/internal DMA missmatches.	mohor	8138d 07h	/ethmac/trunk/rtl/verilog/ethmac.v
76	Interrupts changed in the top file	mohor	8138d 08h	/ethmac/trunk/rtl/verilog/ethmac.v
70	Small fixes.	mohor	8146d 14h	/ethmac/trunk/rtl/verilog/ethmac.v
68	Registered trimmed. Unused registers removed.	mohor	8148d 10h	/ethmac/trunk/rtl/verilog/ethmac.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8148d 11h	/ethmac/trunk/rtl/verilog/ethmac.v
65	Testbench fixed, code simplified, unused signals removed.	mohor	8148d 17h	/ethmac/trunk/rtl/verilog/ethmac.v
63	RxAbort is connected differently.	mohor	8149d 10h	/ethmac/trunk/rtl/verilog/ethmac.v
59	Changes that were lost when updating from 1.11 to 1.14 fixed.	mohor	8149d 13h	/ethmac/trunk/rtl/verilog/ethmac.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8150d 04h	/ethmac/trunk/rtl/verilog/ethmac.v
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8152d 07h	/ethmac/trunk/rtl/verilog/ethmac.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 202

Filtering Options