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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 146

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Rev	Log message	Author	Age	Path
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	8104d 16h	/ethmac/trunk/rtl/verilog
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	8104d 16h	/ethmac/trunk/rtl/verilog
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	8120d 18h	/ethmac/trunk/rtl/verilog
141	Syntax error fixed.	mohor	8123d 12h	/ethmac/trunk/rtl/verilog
140	Syntax error fixed.	mohor	8123d 12h	/ethmac/trunk/rtl/verilog
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	8123d 12h	/ethmac/trunk/rtl/verilog
138	Synchronous reset added.	mohor	8123d 12h	/ethmac/trunk/rtl/verilog
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	8123d 12h	/ethmac/trunk/rtl/verilog
136	Parameter ResetValue changed to capital letters.	mohor	8123d 22h	/ethmac/trunk/rtl/verilog
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	8125d 15h	/ethmac/trunk/rtl/verilog
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	8125d 16h	/ethmac/trunk/rtl/verilog
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	8125d 16h	/ethmac/trunk/rtl/verilog
131	LinkFail signal was not latching appropriate bit.	mohor	8125d 16h	/ethmac/trunk/rtl/verilog
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8125d 17h	/ethmac/trunk/rtl/verilog
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8145d 16h	/ethmac/trunk/rtl/verilog
126	InvalidSymbol generation changed.	mohor	8145d 16h	/ethmac/trunk/rtl/verilog
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	8145d 16h	/ethmac/trunk/rtl/verilog
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8147d 18h	/ethmac/trunk/rtl/verilog
120	Unused files removed.	mohor	8147d 19h	/ethmac/trunk/rtl/verilog
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8147d 19h	/ethmac/trunk/rtl/verilog

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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 146

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