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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 350

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Rev Log message Author Age Path
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4860d 21h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4861d 21h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4862d 23h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4872d 23h /ethmac/trunk/rtl/verilog
338 root 5667d 01h /ethmac/trunk/rtl/verilog
335 New directory structure. root 5724d 07h /ethmac/trunk/rtl/verilog
333 Some small fixes + some troubles fixed. igorm 7172d 21h /ethmac/trunk/rtl/verilog
332 Case statement improved for synthesys. igorm 7186d 02h /ethmac/trunk/rtl/verilog
330 Warning fixes. igorm 7201d 04h /ethmac/trunk/rtl/verilog
329 Defer indication fixed. igorm 7201d 05h /ethmac/trunk/rtl/verilog
328 Delayed CRC fixed. igorm 7201d 05h /ethmac/trunk/rtl/verilog
327 Defer indication fixed. igorm 7201d 05h /ethmac/trunk/rtl/verilog
326 Delayed CRC fixed. igorm 7201d 06h /ethmac/trunk/rtl/verilog
325 Defer indication fixed. igorm 7201d 06h /ethmac/trunk/rtl/verilog
323 Accidently deleted line put back. igorm 7498d 06h /ethmac/trunk/rtl/verilog
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7502d 01h /ethmac/trunk/rtl/verilog
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7502d 05h /ethmac/trunk/rtl/verilog
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7542d 07h /ethmac/trunk/rtl/verilog
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7645d 04h /ethmac/trunk/rtl/verilog
306 Lapsus fixed (!we -> ~we). simons 7646d 02h /ethmac/trunk/rtl/verilog

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