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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 358

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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4777d 08h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4777d 08h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4777d 10h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4777d 11h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4777d 11h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4779d 12h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4783d 18h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4792d 08h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4792d 09h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4793d 09h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4794d 11h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4804d 11h /ethmac/trunk/rtl/verilog
338 root 5598d 13h /ethmac/trunk/rtl/verilog
335 New directory structure. root 5655d 19h /ethmac/trunk/rtl/verilog
333 Some small fixes + some troubles fixed. igorm 7104d 09h /ethmac/trunk/rtl/verilog
332 Case statement improved for synthesys. igorm 7117d 14h /ethmac/trunk/rtl/verilog
330 Warning fixes. igorm 7132d 16h /ethmac/trunk/rtl/verilog
329 Defer indication fixed. igorm 7132d 17h /ethmac/trunk/rtl/verilog
328 Delayed CRC fixed. igorm 7132d 17h /ethmac/trunk/rtl/verilog
327 Defer indication fixed. igorm 7132d 18h /ethmac/trunk/rtl/verilog

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