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[/] [ethmac/] [trunk/] [rtl] - Rev 101

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Rev Log message Author Age Path
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8246d 06h /ethmac/trunk/rtl
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8246d 06h /ethmac/trunk/rtl
97 Small typo fixed. lampret 8270d 03h /ethmac/trunk/rtl
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8274d 03h /ethmac/trunk/rtl
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8274d 06h /ethmac/trunk/rtl
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8274d 06h /ethmac/trunk/rtl
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8279d 04h /ethmac/trunk/rtl
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8280d 07h /ethmac/trunk/rtl
91 Comments in Slovene language removed. mohor 8280d 07h /ethmac/trunk/rtl
90 casex changed with case, fifo reset changed. mohor 8280d 07h /ethmac/trunk/rtl
88 rx_fifo was not always cleared ok. Fixed. mohor 8290d 04h /ethmac/trunk/rtl
87 Status was not latched correctly sometimes. Fixed. mohor 8290d 06h /ethmac/trunk/rtl
86 Big Endian problem when sending frames fixed. mohor 8291d 13h /ethmac/trunk/rtl
85 Log info was missing. mohor 8296d 23h /ethmac/trunk/rtl
84 LinkFail signal was not latching appropriate bit. mohor 8296d 23h /ethmac/trunk/rtl
83 MAC address recognition was not correct (bytes swaped). mohor 8296d 23h /ethmac/trunk/rtl
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8297d 00h /ethmac/trunk/rtl
80 Small fixes for external/internal DMA missmatches. mohor 8301d 03h /ethmac/trunk/rtl
79 RetryCntLatched was unused and removed from design mohor 8301d 03h /ethmac/trunk/rtl
78 WB_SEL_I was unused and removed from design mohor 8301d 03h /ethmac/trunk/rtl

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