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[/] [ethmac/] [trunk] - Rev 150

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Rev Log message Author Age Path
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 8103d 19h /ethmac/trunk
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 8103d 19h /ethmac/trunk
148 Bug when last byte of destination address was not checked fixed. mohor 8103d 19h /ethmac/trunk
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 8103d 19h /ethmac/trunk
146 CarrierSenseLost status is not set when working in loopback mode. mohor 8103d 19h /ethmac/trunk
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 8103d 19h /ethmac/trunk
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 8119d 22h /ethmac/trunk
141 Syntax error fixed. mohor 8122d 15h /ethmac/trunk
140 Syntax error fixed. mohor 8122d 15h /ethmac/trunk
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 8122d 16h /ethmac/trunk
138 Synchronous reset added. mohor 8122d 16h /ethmac/trunk
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 8122d 16h /ethmac/trunk
136 Parameter ResetValue changed to capital letters. mohor 8123d 01h /ethmac/trunk
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 8124d 17h /ethmac/trunk
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 8124d 18h /ethmac/trunk
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).		 mohor 8124d 19h /ethmac/trunk
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 8124d 19h /ethmac/trunk
131 LinkFail signal was not latching appropriate bit. mohor 8124d 19h /ethmac/trunk
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.		 mohor 8124d 20h /ethmac/trunk
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface		 mohor 8124d 20h /ethmac/trunk

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