OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gecko3com_test_chipscope.cdc] - Rev 21

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 system is fully working and tested with big files over 4 Gbyte. there were some smaller bugs and glitches which caused
sometimes a deadlock. they are fixed now.

one was because the fx2 reads the done pin sometimes wrong during a long data
transfer. I don't now if this is because of crosstalk on my prototyping system or fpga internal weakness.
a simple debouncing (read again after 40 ms) did the trick.

changed firmware version to 0.5rc0, basically all features targeted for 0.5 are done.		 nussgipfel 5258d 10h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/gecko3com_test_chipscope.cdc
20 basic synchronous IN (fpga to host) transfer works.

detail changes:
-the scpi command "fpga:data" checks now, if the fpga is configured before it changes the context to the fpga. if the fpga is
not configured, it returns an "EXECUTE ERROR".
in the same way, the main_loop checks if the fpga looses his configuration. it disables the GPIF, switches the context back
to the fx2 if so. this is mainly to avoid undeterministic behaviour if you reconfigure the fpga via jtag.

-introduced the new signal "EOM" end of message from the "usb tmc protokoll interpreter" to the gpif_com module

-changed the GPIF waveform for the FIFO IN transfer to the new scheme.

-implemented the same waveform into the gpif_com_fsm.vhd. works well together.

-bugfixed the gpif_com_test.vhd. sends the new EOM signal, the response message generator works now as it should.

-added the missing AUTHORS README and COPYING (license) files to the core directory.		 nussgipfel 5259d 09h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/gecko3com_test_chipscope.cdc
18 I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.

in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.		 nussgipfel 5270d 19h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/gecko3com_test_chipscope.cdc
14 reorganising and renaming the stuff in these project.

the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb"
to follow the naming in the GECKO3 wiki and to show the IP core interface.

duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings
from unavailable, unused and unconnected pins.

the project is now organised in a way how the IP core and it's parts are beeing used. this means that the
low-level gpif access module is instantiated by the higher level modules and not the other way around.
this will make more sense when more parts of this IP core are finished (planning is finished, they have
to be implemented and tested now).		 nussgipfel 5298d 16h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/usb_tmc_ip_chipscope.cdc

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.