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[/] [ha1588/] [tags/] [v2p0/] [rtl/] [tsu/] [tsu.v] - Rev 78

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78 Prepare for adding new system integration tool support. ash_riple 2457d 13h /ha1588/tags/v2p0/rtl/tsu/tsu.v
68 Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory. ash_riple 4186d 20h /ha1588/tags/v2p0/rtl/tsu/tsu.v
54 Added support for MII interface as well as GMII interface. Updated unit and top-level test cases. edn_walter 4472d 15h /ha1588/tags/v2p0/rtl/tsu/tsu.v
44 Updated TSU testbench. edn_walter 4483d 08h /ha1588/tags/v2p0/rtl/tsu/tsu.v
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4484d 06h /ha1588/tags/v2p0/rtl/tsu/tsu.v
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.
edn_walter 4484d 18h /ha1588/tags/v2p0/rtl/tsu/tsu.v
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.
edn_walter 4485d 15h /ha1588/tags/v2p0/rtl/tsu/tsu.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4485d 18h /ha1588/tags/v2p0/rtl/tsu/tsu.v
34 Added LGPL file header to all copyrighted files. edn_walter 4487d 15h /ha1588/tags/v2p0/rtl/tsu/tsu.v
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4487d 19h /ha1588/tags/v2p0/rtl/tsu/tsu.v
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4488d 12h /ha1588/tags/v2p0/rtl/tsu/tsu.v
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4488d 19h /ha1588/tags/v2p0/rtl/tsu/tsu.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4497d 13h /ha1588/tags/v2p0/rtl/tsu/tsu.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4504d 08h /ha1588/tags/v2p0/rtl/tsu/tsu.v
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 4510d 08h /ha1588/tags/v2p0/rtl/tsu/tsu.v
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4511d 08h /ha1588/tags/v2p0/rtl/tsu/tsu.v
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4511d 14h /ha1588/tags/v2p0/rtl/tsu/tsu.v
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4511d 15h /ha1588/tags/v2p0/rtl/tsu/tsu.v
5 Added dcfifo to store ptp time stamps. ash_riple 4514d 07h /ha1588/tags/v2p0/rtl/tsu/tsu.v
4 Added source code and unit test for TSU. ash_riple 4515d 07h /ha1588/tags/v2p0/rtl/tsu/tsu.v

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